Understanding SAR ADCs: Their Architecture and Comparison with Other ADCs

Abstract: Successive-approximation-register (SAR) analog-to-digital converters (ADCs) represent the majority of the ADC market for medium- to high-resolution ADCs. SAR ADCs provide up to 5Msps sampling rates with resolutions from 8 to 18 bits. The SAR architecture allows for high-performance, low-power ADCs to be packaged in small form factors for today's demanding applications.

This paper will explain how the SAR ADC operates by using a binary search algorithm to converge on the input signal. It also explains the heart of the SAR ADC, the capacitive DAC, and the high-speed comparator. Finally, the article will contrast the SAR architecture with pipeline, flash, and sigma-delta ADCs.