Product Details
Key Features
Applications/Uses
Simplified Block Diagram
Technical Docs
Data Sheet | Low-Power, Arm Cortex-M4 Processor with FPU-Based Microcontroller and Bluetooth 5.2 | Sep 09, 2020 |
Support & Training
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Filtered SearchOur dedicated team of Applications Engineers are also available to answer your technical questions. Visit our support portal .
Key Features
- Ultra-Low-Power Wireless Microcontroller
- Internal 100MHz Oscillator
- Flexible Low-Power Modes with 7.3728MHz System Clock Option
- 512KB Flash and 128KB SRAM
- Optional ECC on One 32KB SRAM Bank
- 16KB Instruction Cache
- Bluetooth 5.2 LE Radio
- Dedicated, Ultra-Low-Power, 32-Bit RISC-V Coprocessor to Offload Timing-Critical Bluetooth Processing
- Fully Open-Source Bluetooth 5.2 Stack Available
- Supports AoA, AoD, LE Audio, and Mesh
- High-Throughput (2Mbps) Mode
- Long-Range (125kbps and 500kbps) Modes
- Rx Sensitivity: -97.5dBm; Tx Power: +4.5dBm
- Single-Ended Antenna Connection (50Ω)
- Power Management Maximizes Battery Life
- 2.0V to 3.6V Supply Voltage Range
- Integrated SIMO Power Regulator
- Dynamic Voltage Scaling (DVS)
- 23.8μA/MHz Active Current at 3.0V
- 4.4μA at 3.0V Retention Current for 32KB
- Selectable SRAM Retention + RTC in Low-Power Modes
- Multiple Peripherals for System Control
- Two High-Speed SPI Master/Slave
- Three High-Speed I2C Master/Slave (3.4Mbps)
- Four UART, One I2S Master/Slave
- 8-Input, 10-Bit Sigma-Delta ADC 7.8ksps
- Four Micro-Power Comparators
- Timers: Two 32-Bit, Two LP, Two Watchdog Timers
- 1-Wire® Master
- Four Pulse Train (PWM) Engines
- RTC with Wake-Up Timer
- Up to 52 GPIOs
- Security and Integrity
- Available Secure Boot
- TRNG Seed Generator
- AES 128/192/256 Hardware Acceleration Engine
Applications/Uses
- Asset Tracking
- Fitness/Health and Medical Wearables
- Hearables
- Industrial Sensors
- Wireless Computer Peripherals and I/O Devices
Description
The device offers large onboard memory with 512KB flash and 128KB SRAM, with optional error correction coding on one 32KB SRAM bank. This 32KB bank can be optionally retained in backup mode. An 8KB user OTP area is available and 8 bytes are retained, even during power-down.
Many high-speed interfaces are supported on the device including multiple QSPI, UART, and I2C serial interfaces, plus one I2S port for connecting to an audio codec. An eight-input, 10-bit ADC is available to monitor analog input from external analog sources.
The device is available in an 81 CTBGA (9 x 9, 8mm x 8mm, 0.8mm pitch) package.
Technical Docs
Data Sheet | Low-Power, Arm Cortex-M4 Processor with FPU-Based Microcontroller and Bluetooth 5.2 | Sep 09, 2020 |
Support & Training
Search our knowledge base for answers to your technical questions.
Filtered SearchOur dedicated team of Applications Engineers are also available to answer your technical questions. Visit our support portal .